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دانلود کتاب MicroSystem Based on SiP Technology

میکروسیستم مبتنی بر فناوری SiP
عنوان فارسی

میکروسیستم مبتنی بر فناوری SiP

عنوان اصلیMicroSystem Based on SiP Technology
ناشر
نویسندهSuny Li
ISBN 9811900825, 9789811900822
سال نشر
زبانEnglish
تعداد صفحات867
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Preface
Brief Introduction of the New Book
Contents
About the Author
Part I Concept and Technology
1 From Moore\'s Law to Function Density Law
1.1 Moore\'s Law
1.2 Two Problems Facing Moore\'s Law
1.2.1 Reduction of Micro-Scale
1.2.2 Consumption of Macro-Resources
1.3 Function Density Law
1.3.1 Description of Function Density Law
1.3.2 Six Level Classification of Electronic Systems
1.3.3 Comparison of Moore\'s Law and Function Density Law
1.3.4 Applications of Function Density Law
1.3.5 Extension of Function Density Law
1.4 General Function Density Law
1.4.1 System Space Definition
1.4.2 Earth Space and Human Cosmic Space
1.4.3 General Function Density Law
2 From SiP to Si3P
2.1 Concept Deepening: From SiP to Si3P
2.2 Integration of Si3P
2.2.1 Chip Level Integration
2.2.2 PCB Level Integration
2.2.3 Package Level Integration
2.2.4 Summary of Integration
2.3 Interconnection of Si3P
2.3.1 Interconnection of EM
2.3.2 Interconnection of Thermo
2.3.3 Interconnection of Force
2.3.4 Summary of Interconnection
2.4 Intelligence of Si3P
2.4.1 System Function Definition
2.4.2 Product Application Scenario
2.4.3 Testing and Debugging
2.4.4 Software and Algorithm
2.4.5 Summary of Intelligence
2.5 Summary of Si3P
2.5.1 History Review of Integration
2.5.2 Associative Metaphor
2.5.3 Prospect Forecast
3 SiP and MicroSystem
3.1 SiP Technology
3.1.1 Definition of SiP Technology
3.1.2 SiP and Related Technologies
3.1.3 SiP or SOP?
3.1.4 Application Fields of SiP Technology
3.1.5 Selection of SiP Process and Materials
3.2 MicroSystem
3.2.1 Natural and Man-Made System
3.2.2 Definition and Features of System
3.2.3 New Definition of MicroSystem
4 From 2D to 4D Integration
4.1 Development of Integration Technology
4.1.1 Scale of Integration
4.1.2 One-Step Integration and Two-Step Integration
4.1.3 Classified Naming for Package Internal Integration
4.2 2D Integration Technology
4.2.1 Definition of 2D Integration
4.2.2 Application of 2D Integration
4.3 2D+ Integration Technology
4.3.1 Definition of 2D+ Integration
4.3.2 Application of 2D+ Integration
4.4 2.5D Integration Technology
4.4.1 Definition of 2.5D Integration
4.4.2 Application of 2.5D Integration
4.5 3D Integration Technology
4.5.1 Definition of 3D Integration
4.5.2 Application of 3D Integration
4.6 4D Integration Technology
4.6.1 Definition of 4D Integration
4.6.2 Application of 4D Integration
4.6.3 The Significance of 4D Integration
4.7 Cavity Integration Technology
4.7.1 Definition of Cavity Integration
4.7.2 Application of Cavity Integration
4.8 Planar Integration Technology
4.8.1 Definition of Planar Integration
4.8.2 Application of Planar Integration
4.9 Summary of Integration Technology
5 SiP and Advanced Packaging Technology
5.1 SiP Substrate and Package
5.1.1 Organic Substrate
5.1.2 Ceramic Substrate
5.1.3 Silicon Substrate
5.2 Advanced Packaging Technology
5.2.1 TSV Technology
5.2.2 RDL Technology
5.2.3 IPD Technology
5.2.4 Chiplet Technology
5.3 Advanced Packaging Technology
5.3.1 Advanced Packaging Based on XY Plane Extension
5.3.2 Advanced Packaging Based on Z-Axis Extension
5.3.3 Summary of Advanced Packaging Technology
5.3.4 Elements: RDL, TSV, Bump and Wafer
5.4 Features and Design Requirements of HDAP
5.4.1 Features of Advanced Packaging (HDAP)
5.4.2 Relationship Between Advanced Packaging and SiP
5.4.3 Advanced Packaging and SiP Design Requirements
References and Notes
References
Notes
Part II Design and Simulation
6 SiP Design and Simulation Platform
6.1 Development of SiP Design Technology
6.2 Two Sets of SiP Design Flow
6.3 General SiP Design Flow
6.3.1 Schematic Design Input
6.3.2 Multi-layout Design Collaboration
6.3.3 Functions of SiP Layout Design
6.4 SiP Design Flow Based on HDAP
6.4.1 XSI-Design Integration and Net Optimization Tool
6.4.2 XPD-HDAP Layout Design Tool
6.5 Which Design Flow is Suitable for Designers?
6.6 SiP Simulation and Verification Flow
6.6.1 Electromagnetic Simulation
6.6.2 Thermal Simulation
6.6.3 Mechanical Simulation
6.6.4 Design Verification
6.7 Advanced Natures of SiP/HDAP Platform
7 Central Library Creation and Management
7.1 Structure of Central Library
7.2 Dashboard Introduction
7.3 Schematic Symbol Creation
7.4 Layout Cell Creation
7.4.1 Bare Chip Cell Creation
7.5 Create Bare Chip Padstack
7.6 Create Bare Chip Cell
7.6.1 SiP Package Cell Creation
7.7 Part Creation and Application
7.7.1 Mapping Part
7.7.2 Create Cell from Part Data
7.8 Central Library Maintenance and Management
7.8.1 Common Settings of Central Library
7.8.2 Import and Export Central Library Data
8 SiP Schematic Design Input
8.1 Netlist Input
8.2 Schematic Design Input
8.2.1 Schematic Tool Introduction
8.2.2 Create Schematic Project
8.2.3 Schematic Basic Operation
8.2.4 Schematic Design Check
8.2.5 Design Package
8.2.6 Output Partlist
8.2.7 Schematic Chinese Menu and Chinese Input
8.3 Schematic Input Based on DataBook
8.3.1 Introduction to DataBook
8.3.2 How to Use DataBook
8.3.3 Verify and Update Component Properties
8.4 File Input and Output
8.4.1 Common Input and Output
8.4.2 Output to Simulation Tool
9 Layout Creation and Setup
9.1 Create Layout Template
9.1.1 Layout Template Definition
9.1.2 Create SiP Layout Template
9.2 Create Layout Project
9.2.1 Create New SiP Project
9.2.2 Enter Layout Design Environment
9.3 Layout Settings and Operations
9.3.1 Layout License Control
9.3.2 Mouse Operation Methods
9.3.3 Four Common Operating Modes
9.3.4 Display Control
9.3.5 Editor Control
9.3.6 Smart Cursor Tips
9.4 Layout Design
9.4.1 Component Placement
9.4.2 View Schematic in Layout
9.5 Package Pin Optimization
9.6 Layout Chinese Input
10 Management of Design Rules
10.1 Constraint Manager
10.2 Scheme
10.2.1 Create Scheme
10.2.2 Apply Scheme in Layout Design
10.3 Net Class
10.3.1 Create Net Class and Assign Nets to Net Class
10.3.2 Define Net Class Rules
10.4 Clearance
10.4.1 Create and Setup Clearance Rules
10.4.2 General Clearance Rule
10.4.3 Net Class to Net Class Clearance Rule
10.5 Constraint Class
10.5.1 Create Constraint Class and Assign Nets
10.5.2 Classification of Electrical Constraints
10.5.3 Edit Constraint Group
10.6 Constraint Manager and Layout Data Interaction
10.6.1 Update Layout Data
10.6.2 Interact with Layout Data
10.7 Rule Setting Instances
10.7.1 Equal Length Setting
10.7.2 Differential Pairs Setting
10.7.3 Z-Axis Clearance Setting
11 Wire Bonding Design in Detail
11.1 Overview of Wire Bonding
11.2 Bond Wire Model
11.2.1 Bond Wire Model Definition
11.2.2 Bond Wire Model Parameters
11.3 Wire Bonding Toolbar and Its Application
11.3.1 Add Bond Wire Manually
11.3.2 Move, Push and Rotate Bond Finger
11.3.3 Generate Bond Wire Automatically
11.3.4 Add Bond Wire Through Guide
11.3.5 Add Power Ring
11.4 Bond Wire Rules Setting
11.4.1 Settings for Component
11.4.2 Settings for Die Pins
11.4.3 Add Multiple Bond Wires Between Die Pin and Bond Finger
11.4.4 Fan Out from Single Die Pin to Multiple Bond Fingers
11.4.5 Bond Multiple Die Pins to One Bond Finger
11.4.6 Die to Die Bonding
11.5 Wire Model Editor and Wire Instance Editor
12 Cavity, Chip Stack and TSV Design
12.1 Cavity Design
12.1.1 Definition of Cavity
12.1.2 Cavity Creation
12.1.3 Place Component into Cavity
12.1.4 Bonding in Cavity
12.1.5 Embedding Chip into Substrate with Cavity
12.1.6 Embedding Chip by Adding Cavity to Die Cell
12.2 Chip Stack Design
12.2.1 The Concept of Chip Stack
12.2.2 Chip Stack Creation
12.2.3 Stack Chips Side by Side
12.2.4 Chip Stack Adjustment and Bonding
12.2.5 Chip and Cavity Combination Design
12.3 Concept and Design of 2.5D TSV
12.4 Concept and Design of 3D TSV
12.4.1 Concept of 3D TSV
12.4.2 3D TSV Cell Creation
12.4.3 Pin Alignment Principle Between Chip Stack
12.4.4 3D TSV Stacking and Interconnection
12.4.5 3D Pin Model Setup
12.4.6 Net Optimization and Route
12.4.7 DRC Check and Complete 3D TSV Design
13 RDL and Flip Chip Design
13.1 Concept and Applications of RDL
13.1.1 Fan-In RDL
13.1.2 Fan-Out RDL
13.2 Concept and Features of Flip Chip
13.3 RDL Design
13.3.1 Build Bare Die and RDL Library
13.3.2 RDL Schematic Design
13.3.3 RDL Layout Design
13.4 Flip Chip Design
13.4.1 Flip Chip Schematic Design
13.4.2 Flip Chip Layout Design
14 Route and Plane
14.1 Route
14.1.1 Route Overview
14.1.2 Manual Route
14.1.3 Semi-auto Route
14.1.4 Auto Route
14.1.5 Differential Pair Route
14.1.6 Length Control Route
14.1.7 Circuit Copy
14.2 Plane
14.2.1 Definition of Plane
14.2.2 Plane Setting
14.2.3 Plane Shape and Plane Data
14.2.4 Generate Outgassing Voids
14.2.5 Verify Plane Data
15 Embedded Passives Design
15.1 Development of Embedded Technology
15.1.1 Discrete Embedded Technology
15.1.2 Planar Embedded Technology
15.2 Process and Materials for Embedded Passive
15.2.1 Embedding Processes
15.2.2 Materials
15.2.3 Nonlinear Characteristics of Resistance Materials
15.3 Automatic Synthesis of Passive Devices
15.3.1 Prepare for Automatic Synthesis
15.3.2 Automatic Synthesis of Resistors
15.3.3 Automatic Synthesis of Capacitor
15.3.4 Synchronization of Layout and Schematic
16 RF Circuit Design
16.1 RF SiP Technology
16.2 RF Design Flow
16.3 Configuration of RF Component Library
16.3.1 Import RF Symbols into Design Central Library
16.3.2 Central Library Partition Search Path Setting
16.4 RF Schematic Design
16.4.1 RF Schematic Toolbar
16.4.2 RF Schematic Input
16.5 RF Parameters Transfer
16.6 RF Layout Design
16.6.1 RF Layout Toolbox
16.6.2 Three Types of RF Unit
16.6.3 Draw and Edit Meander
16.6.4 Create User-Defined RF Units
16.6.5 Via Add Function
16.6.6 Introduction to RF Group
16.6.7 Auto Arrange Function
16.6.8 Connect RF Units with Bond Wire
16.7 Transfer Data with RF Simulation Tools
16.7.1 Connect RF Simulation Tools
16.7.2 Schematic RF Data Transfer
16.7.3 Layout RF Data Transfer
17 Rigid-Flex Circuits and 4D SiP Design
17.1 Introduction to Rigid-Flex Circuits
17.2 Rigid-Flex Circuits Design
17.2.1 Design Flow of Rigid-Flex Circuits
17.2.2 Layer Type Unique to Rigid-Flex Circuits
17.2.3 Rigid-Flex Circuits Design Steps
17.3 Complex Substrate Technology
17.3.1 Definition of Complex Substrate
17.3.2 Application of Complex Substrate
17.4 SiP Design Based on 4D Integration
17.4.1 4D SiP Substrate Definition
17.4.2 4D SiP Design Flow
17.5 Significance of 4D SiP Design
18 Multi-layout Project and Concurrent Design
18.1 Multi-layout Project
18.1.1 Multi-layout Project Design Requirements
18.1.2 Multi-layout Project Design Flow
18.2 Schematic Multi-person Concurrent Design
18.2.1 Schematic Concurrent Design Ideas
18.2.2 Operation Method of Schematic Concurrent Design
18.3 Layout Multi-person Real-Time Concurrent Design
18.3.1 Configuration of Layout Real-Time Concurrent Software
18.3.2 Apply Layout Real-Time Concurrent Design
19 SiP Design Flow Based on Advanced Package (HDAP)
19.1 Advanced Package Design Flow Introduction
19.1.1 Technical Indicators for HDAP Design Environment
19.1.2 HDAP Design Flow
19.1.3 Design Task: HBM (3D + 2.5D)
19.2 XSI Design Environment
19.2.1 Design Data Preparation
19.2.2 Introduction to XSI Working Windows
19.2.3 Create Projects and Design then Add Components
19.3 Add Bare Chip Device
19.3.1 Optimize Net Connection Through XSI
19.3.2 Layout Template Selection
19.3.3 Design Data Transfer
19.4 XPD Design Environment
19.4.1 Interposer Data Synchronization Check
19.4.2 Interposer Layout and Routing
19.4.3 Substrate Data Synchronization Check
19.4.4 Substrate Layout and Routing
19.5 3D Digital Prototype Simulation
19.5.1 The Concept of Digital Prototype
19.5.2 Introduction to 3D View Environment
19.5.3 Build HDAP Digital Prototype Model
20 Design Check and Production Data Output
20.1 Online DRC
20.2 Batch DRC
20.2.1 DRC Settings
20.2.2 Connectivity and Special Rules
20.2.3 Batch DRC Scheme
20.3 Introduction to Hazard Explorer
20.4 Design Library Check
20.5 Production Data Classification
20.6 Gerber and Drill Data Output
20.6.1 Drill Data Output
20.6.2 Gerber Machine Format
20.6.3 Gerber Data Output
20.6.4 Import and Check Gerber Data
20.7 GDS File and Color Map Output
20.7.1 GDS File Output
20.7.2 Color Map Output
20.8 Other Production Data Output
20.8.1 Component and Bond Wire Coordinate Output
20.8.2 DXF File Output
20.8.3 Layout Design Status Output
20.8.4 BOM Output
21 SiP Simulation and Verification
21.1 Overview of SiP Simulation and Verification
21.2 Signal Integrity Simulation
21.2.1 Introduction to HyperLynx SI
21.2.2 Signal Integrity Simulation Example
21.3 Power Integrity Simulation
21.3.1 Introduction to HyperLynx PI
21.3.2 Power Integrity Simulation Example
21.4 Thermal Simulation
21.4.1 Introduction to HyperLynx Thermal
21.4.2 Thermal Simulation Example
21.4.3 Introduction to FloTHERM Software
21.4.4 Introduction to T3Ster
21.5 Advanced 3D Solver
21.5.1 Introduction to HyperLynx Full-Wave Solver
21.5.2 Introduction to HyperLynx Fast 3D Solver
21.6 Simulation of Digital-Analog Mixed Circuit
21.7 Electrical Rules Verification
21.7.1 Introduction to HyperLynx DRC
21.7.2 Examples of Electrical Verification
21.8 HDAP Physical Verification
21.8.1 Introduction to Calibre 3DSTACK
21.8.2 HDAP Physical Verification Example
References and Notes
References
Notes
Part III Projects and Cases
22 Mass Storage Chip Design Case
22.1 Application of Mass Storage Chip in Space
22.2 Feasibility Analysis of SiP Application
22.2.1 Bare Chip Selection
22.2.2 Selection of Design and Simulation Tools
22.2.3 Selection of Manufacturing and Testing Factory
22.3 Design of Mass Storage Chip
22.3.1 Scheme Design
22.3.2 Detailed Design
22.4 Packaging and Testing of Mass Storage Chip
22.4.1 Packaging
22.4.2 Machine Test
22.4.3 System Test
22.4.4 Follow-Up Testing and Cost Ratio
22.5 Comparison of Technical Parameters
23 SiP Project Planning and Design Case
23.1 SiP Project Planning
23.1.1 Characteristics and Applicability of SiP
23.1.2 Factors That Need to Be Identified for SiP Projects
23.2 Design Rule Import
23.2.1 Project Requirements and Scheme Analysis
23.2.2 Implementation Scheme of SiP
23.3 The Design of SiP Products
23.3.1 Symbol and Cell Library Creation
23.3.2 Schematic Design
23.3.3 Layout Design
23.3.4 Product Packaging and Testing
24 2.5D TSV Technology and Design Case
24.1 2.5D Integration Requirement
24.2 Comparison of Traditional Packaging with 2.5D
24.2.1 Flip Chip Process
24.2.2 Wire Bonding Process
24.2.3 Advantage and Disadvantage of Traditional Package and 2.5D
24.3 2.5D TSV Interposer Design
24.3.1 2.5D TSV Interposer Package Structure
24.3.2 2.5D Interposer Package Design
24.4 Process Comparison of Interposer and Organic Substrates
24.4.1 Si Interposer
24.4.2 Glass Interposer
24.4.3 Organic Substrate
24.4.4 Process Capability Comparison
24.5 Mask Porcess Introduction
24.6 2.5D Interposer Design, Simulation and Manfacture
24.6.1 Package Structure Design
24.6.2 Package Layout, Signal and Structure Simulation
24.6.3 Production Data Tape Out and Mask Preparation
24.6.4 Interposer Manufacture and Assembly
25 Digital T/R Module SiP Design Case
25.1 Introduction to Radar System
25.2 SiP Technology Adoption
25.3 Design of Digital T/R Module
25.3.1 Function Introduction of Digital T/R Module
25.3.2 Structure and Principle Design of Digital T/R
25.3.3 Digital T/R Module SiP Layout Design
25.4 Metal Shell and Integrated Packaging Design
26 MEMS Verification SiP Design Case
26.1 Project Introduction
26.2 SiP Scheme Design
26.3 SiP Circuit Design
26.3.1 Library Build and Schematic Design
26.3.2 SiP Layout Design
26.4 Assembly and Testing Board
27 Rigid-Flex SiP Design Case
27.1 Introduction of Rigid-Flex Substrate
27.2 RF Front-End Architecture and RF SiP Scheme
27.2.1 System Architecture of Micro Base Station RF Front-End
27.2.2 RF SiP Package Design
27.2.3 RF SiP Substrate Stack-Up Design
27.3 Electrical Simulation of the Rigid-Flex Substrate
27.3.1 Design and Simulation of Signal Transmission
27.3.2 Design and Simulation of Power Distribution Network
27.4 Thermal Management Evaluation of RF SiP
27.4.1 Thermal Resistance Analysis of the Package Structure
27.4.2 Thermal Management Simulation of RF SiP
27.5 Assembly Flow of RF SiP
28 RF System Integrated SiP Design Case
28.1 RF System Integration Technology
28.1.1 RF System Introduction
28.1.2 Miniaturization Trend for RF System Integration
28.1.3 RF SiP Versus RF SoC
28.2 Design and Simulation of RF SiP
28.2.1 RF SiP Structure Design
28.2.2 RF SiP Electrical Design and Simulation
28.2.3 Thermal Management of RF SiP
28.3 Assembly and Test of RF SiP
28.3.1 Assembly of RF SiP
28.3.2 RF SiP Testing
29 PoP RF SiP Design Case
29.1 Introduction to PoP Technology
29.2 RF System Architecture and Indicators
29.3 RF SiP Structure and Substrate Design
29.3.1 Structure Design
29.3.2 Substrate Design
29.4 Signal Integrity and Power Integrity Simulation
29.4.1 Signal Integrity (SI) Simulation
29.4.2 Power Integrity (PI) Simulation
29.5 Thermal Design Simulation
29.6 Assembly and Testing
30 SiP Production Data Processing Case
30.1 LTCC, Thick Film and Heterogeneous Integration
30.1.1 LTCC Technology
30.1.2 Thick Film Technology
30.1.3 Heterogeneous Integration Technologies
30.2 Gerber and Drill Data Generation
30.2.1 Gerber Data Generation and Checking
30.2.2 Drill Data Generation and Comparison
30.3 Layout Panel Generation
30.4 Multiple Masks Generation
30.4.1 Mask Generator
30.4.2 Examples of Mask Generation
References
References
Postscript and Thanks

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